A separate note regarding VGA51 interfacing and operation.
The VGA51 design uses internal ram configuration which allows seamless access to video RAM with no need to wait till blanking. It is possible thanks for the way dual ported sram inside the VGA51 chip is used which have been organized where simultaneous write by user and read by VGA control core is provided. If read/write happens at the exact same time, currently the monitor will display "previous" pixel until next frame when new data is accounted for. This way in less powerful systems like Z80 or MCS51 based, the application do not have to wait till blanking time to write data to video ram, instead it can access it anytime.
Still more powerful systems like x86 based cards can monitor blanking interrupt (which VGA51 provides) and use it to synchronize video ram page writes to achieve smooth graphics animations. The theoretical VGA51 fpga chip write/read bandwidth is 25MHz. Achieving this number very much depends from the interface design which may limit this speed. However, for S100 bus for example it seem to leave plenty of room.
Currently fabricated, incoming early next week ISA samples of VGA51 will allow me to benchmark it when used in couple of my ISA equipped PC-AT clones running bus up to 8 and 16MHz rate. The benchmark results will be posted on VGA51 website as well as shared here.